Exemplary embodiments relate to the block decoder of a semiconductor memory device and, more particularly, to the block decoder of a semiconductor memory device.
Recently, there is an increasing demand for semiconductor memory devices which can be electrically programmed and erased and which do not require the refresh function of rewriting data at specific intervals. In order to develop high-capacity memory devices capable of storing a large amount of data, research is being done on technologies for improving the degree of integration of memory devices. To this end, active research is being carried out on flash memory.
Flash memory is chiefly divided into NAND type flash memory and NOR type flash memory. The NOR type flash memory has an excellent random access time characteristic because memory cells are independently coupled to bit lines and word lines. The NAND type flash memory is excellent in terms of the degree of integration because a plurality of memory cells is coupled together in series and so each cell string requires, for example, only one contact. Accordingly, the NAND type flash memory may be used in high integration nonvolatile memory.
In general, a flash memory device includes a block decoder for selecting a memory cell array on a block basis in order to perform a program, a read, and an erase operation.
FIG. 1 is a circuit diagram of a flash memory device for illustrating a known block decoder.
Referring to FIG. 1, a NAND gate ND1 logically combines received address signals XA, XB, XC, and XD, and a NAND gate ND2 logically combines a program precharge signal PGMPREb and the output signal of the NAND gate ND1. When at least one or more of the address signals XA, XB, XC, and XD are in a low level, the NAND gate ND1 outputs a signal of a high level. When one or more of the program precharge signal PGMPREb and the output signal of the NAND gate ND1 are in a low level, the NAND gate ND2 outputs a signal of a high level. Additionally, Vcc represents a power source, Vss represents a around power source, GDSL is a global drain selection line, and GSSL is a global source selection line.
A NAND gate ND3 logically combines a block enable signal EN and the output signal of the NAND gate ND2. When the block enable signal EN is in a low level, the NAND gate ND3 outputs a signal of a high level, and so a transistor N2 is turned on. Accordingly, a node Q1 is reset.
A transistor N1 is turned on in response to a precharge signal PRE so that the output signal of the NAND gate ND2 is supplied to the node Q1. Here, a potential of the node Q1 serves as a block selection signal BLKWL. Meanwhile, transistors N3 and N4 are turned on in response to first and second control signals GC and GB of a pumping voltage (Vpp) level, respectively, and so the pumping voltage Vpp is supplied to the node Q1. In response to the potential of the node Q1 (that is, the block selection signal BLKWL), a block switch 20 is operated, and so global word lines GWL<31:0> and the word lines of a memory cell array 30 are connected.
FIG. 2 shows the arrangement of signal lines used in the block decoder circuit of FIG. 1.
Referring to FIG. 2, according to an example, a plurality of metal lines for receiving signals to control a block decoder is arranged beside a plurality of memory blocks (for example, 2048). From among the metal lines, metal lines for receiving address signals XA<3:0>, XB<7:0>, XC<7:0>, and XD<7:0> are used to receive coding signals to select a memory block and composed of 28 lines. Furthermore, metal lines for receiving first and second control signals GB<7:0> and GC<7:0> obtained by decoding the address signals XB<7:0> and XC<7:0> are arranged in a region adjacent to the plurality of memory blocks. Here, assuming that the line width of each of the metal lines for receiving the first and second control signals GB<7:0> and GC<7:0> is 0.5 μm and the interval between the metal lines is 0.5 μm, a total space of 16 μm is required.